1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a wiring layer in contact with an underlying conductive layer which is partially exposed through a contact hole formed in an insulating film.
2. Description of the Prior Art
Recently, semiconductor devices have been more micropatterned and packing density has increased. Along with this, the manufacturing process has become increasingly complicated. For example, a thick insulating film of a multilayer structure is formed on a semiconductor substrate having many element regions formed therein, contact holes are formed in the insulating film so as to expose the element regions, respectively, and a wiring layer is deposited to contact each element region through each contact hole.
From the viewpoints of high packing density and micropatterning of semiconductor devices, each element region formed in the semiconductor substrate must be miniaturized. Furthermore, the contact holes exposing the element regions must be miniaturized and formed as accurately as possible. The most advanced technique now available for forming such a contact hole is anisotropic etching such as reactive ion etching (RIE). As is well known, a lateral etching or an undercut does not occur in anisotropic etching. As a result, a contact hole having substantially the same shape as that of an opening of a mask used, that is, a contact hole having a steep side wall can be formed in an insulating film.
However, even if a small contact hole is formed by anisotropic etching, a problem occurs when a wiring layer is deposited therein. The problem will now be described with reference to FIG. 1 which shows an enlarged section of an n-channel MOS transistor. The semiconductor device shown in FIG. 1 has a p-type substrate 1. Source and drain regions 3 and 4 are formed in an island region isolated by a field oxide film 2. A channel stop layer 5 is formed under the field oxide film 2. A gate electrode 6 is formed through a gate oxide film 7 on part of a surface of the substrate 1 which corresponds to an area between the source and drain regions 3 and 4. A thick insulating film 8 of a multilayer structure is formed to cover the entire surface of the structure. A contact hole 9 is formed in the insulating film 8, partially exposing the drain region 4. If the contact hole 9 is formed by the RIE, a side wall 9a thereof becomes steep, that is, substantially vertical. The contact hole 9 is formed as small as possible (e.g., 1.5 .mu.m square or less) for micropatterning of the semiconductor device.
When aluminum 10 is deposited to form an electrode wiring layer on the drain region 4 through the small contact hole 9 having the steep side wall 9a, an aluminum overhang 10a is formed over the contact hole 9. Aluminum is not substantially deposited on the drain region 4 and the side wall 9a or it is deposited very thinly as shown by portions indicated by reference numerals 10b or 10c. When aluminum is deposited in this manner, the overhang 10a grows to contact each other and a hollow portion 11 is formed in the aluminum layer 10 in the contact hole 9, as shown in FIG. 1. Once this occurs, aluminum cannot be deposited on a bottom surface of the hollow portion even if an aluminum layer 10' is further formed on the aluminum layer 10.
It is apparent that a satisfactory electrode wiring layer cannot be obtained by patterning the aluminum layer 10 having the hollow portion 11.
This problem also occurs in contacting the wiring layer with another wiring layer through the contact hole formed in an insulating film.
In order to solve the above problem, a method has been proposed to deposit aluminum while the substrate is heated. However, similar to the above-mentioned case, only a thin aluminum layer is deposited on a side wall of a contact hole. Therefore, a semiconductor device having an aluminum film as an electrode deposited in this manner has low reliability.